The present invention relates to the field of integrated circuits, and more particularly, to a device for controlling a power supply in an integrated circuit comprising electrically programmable non-volatile memory elements.
In the new submicron technologies, the oxide thicknesses are very small, for example 25, 55 or 70 angstroms. An oxide with a thickness of 35 angstroms cannot withstand a voltage over 2 volts. An oxide with a thickness of 55 or 70 angstroms cannot withstand a voltage over 4 volts. Thus, with the new submicron technologies, the integrated circuits receive a lower logic supply voltage at a level optimized to give the best response time in terms of speed while ensuring the reliability of the circuit with protection of the oxides.
In certain integrated circuits, it is possible to have parts of the circuit that use different oxide thicknesses. For improved performance, it may be planned that each part will receive the corresponding optimum supply voltage. It is possible for example to have an integrated circuit with one part that is supplied at 3.3 volts while the other part is supplied at 1.8 volts depending on the thickness of the oxides in each part. Usually, the integrated circuit then receives an external logic supply voltage that is the highest supply level, i.e., 3.3 volts in the example. A voltage divider is provided in the circuit to provide the lowest supply level, 1.8 volts in the example. This divider is such that it is capable of withstanding the highest voltage level.
Integrated circuits based on submicron technologies may comprise an electrically programmable non-volatile memory, such as for example, EEPROM, EPROM, flash EPROM or other similar memories. Memories of this kind use voltage levels, for their programming, that are greater than the logic supply voltages of the integrated circuits. These programming voltage levels depend essentially on the technology considered.
An electrically programmable non-volatile memory element usually comprises at least one floating-gate transistor. The programming of a 0 or a 1 in this element is obtained by the application of appropriate programming voltages to the gate, the drain, the source and the well connection (substrate) of this transistor. In a typical example of an integrated circuit based on submicron technology, the programming voltage levels are 5 volts (drain), 9 volts (gate) and ground (source).
To program these memory elements, it is therefore necessary to have available at least one high voltage that is higher than the logic supply voltages of the integrated circuit. The programming voltage levels needed are produced internally, from this high voltage, by circuitry for the selection and programming of the memory elements. This circuitry includes, for example, a voltage adder or multiplier type circuit.
The integrated circuits typically receive this high voltage permanently at an external pin. Some of the elements of the selection and programming circuitry, and especially their oxides, may receive this high voltage permanently. Depending on the other voltage levels that are applied to them, they may therefore have an excessively high potential at their terminals, and this may be the case frequently or almost permanently. In submicron technologies, the oxides are particularly thin. Even when using the greatest thickness available in the technology considered, it would have to be ensured that each oxide to be protected has a cascode type protection element so that the reliability is not reduced. For reasons of complexity, functionality and cost, an approach of this kind is not satisfactory.
In view of the foregoing background, an object of the present invention is to improve the reliability of such integrated circuits based on submicron technology, with electrically programmable non-volatile memories, by an overall protection device designed at the level of the high voltage pin.
This and other objects, advantages and features of the present invention are provided by a power supply control device such that the elements of the selection and programming circuit associated with the non-volatile memory elements are powered by the logic power voltage at least outside the programming cycle. With a power control device according to the present invention, the selection and programming circuit associated with the non-volatile memory elements are subjected to programming voltage levels only during the programming cycles. For the remainder of the time, they receive the lower level logic power voltage without in any way endangering the submicron oxides. Thus, the time of exposure to the programming voltage levels is significantly reduced. The reliability of the integrated circuits comprising a power supply control device of this kind is greatly improved.
A power supply control device according to the present invention has two voltage selector switches, one to switch over the high voltage and the other to switch over the logic supply voltage to a power supply input node of the selection and programming circuitry associated with the memory elements. These selection switches are controlled in a complementary way by a voltage level translator connected between the high voltage and ground. This translator is controlled by a binary control signal generated internally by the integrated circuit. The active level of this control signal, used to switch over the high voltage, may correspond to a cycle for writing elements of the non-volatile memory. Outside the writing cycle, this control signal is at its inactive level, which is the supply voltage that is switched over to the input supply node of the selection and programming circuitry.
A cycle for writing memory elements typically comprises, for each programming address, a programming operation followed by a read verification. The write signal remains active only during the time of the write cycle, with read and address changing control signals being used to reduce the time of exposure to the high voltages.
In one embodiment, the level translator is sized so that it can switch over at very high speed, so that it is possible to switch over the high voltage at each change in programming address, to carry out the programming operation at this address and then switch the supply voltage over during the read verification of this programming operation. Thus, the time of exposure to the high voltage is reduced to the maximum.
The invention therefore relates to an integrated circuit comprising electrically programmable non-volatile memory elements and an associated selection and programming circuitry. The integrated circuit includes as supply voltages, a ground reference voltage, at least one logic supply voltage and a high voltage. The high voltage is used to give the voltage levels needed for the programming of one or more non-volatile memory elements. According to the present invention, this integrated circuit furthermore comprises a voltage control device applied to a power input node of the selection and programming circuitry to apply either the high voltage or a logic supply voltage as a function of a programming control signal.